The Ultimate Chiplet System

The Ultimate Chiplet Interconnect. Period.

Eliyan’s Interconnect technology built with standard organic chip packaging delivers the same performance as advanced packaging technology, and enables The Ultimate Chiplet Systems at a fraction of total cost of ownership. Without the downsides of advanced packaging, you achieve higher number of cores, compute performance, test coverage, and yield.

Technology

The transition from monolithic chips into discrete chiplets results in more powerful systems. And the industry is no longer depending on Moore’s Law to provide a path to higher performance, and lower energy at a reasonable cost and complexity. The race to chiplets has put the spotlight squarely on interconnects. Chiplet configurations require new technology optimized to deliver high bandwidth, low latency, and low power. Today, the Universal Chiplet Interconnect Express (UCIe) specification has defined these interconnects, enabling an open ecosystem and ubiquitous interconnect at the package level.

That’s where Eliyan comes in. NuLink™, the Eliyan interconnect solution, delivers performance and power/area efficiency that no other technology can offer. Our exclusive trade secrets and patent-protected technologies deliver a UCIe compliant interconnect at twice the bandwidth and half the power.

How is this possible? Because we have been at this for years, long before the industry standards were established. Inventing NuLink technology, incrementally improving it over the years, and taking it to volume production, have enabled us to achieve unprecedented characteristics.

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Pioneering BoW

A Breakthrough Die-to-Die Interconnect

In 2018, Eliyan CEO Ramin Farjadrad proposed Bunch of Wires (BoW), a superior chiplet interconnect architecture based on NuLink, at the Open Compute Project (OCP). The NuLink architecture leveraged cross-technology innovations to deliver the highest bandwidth and lowest latency, at best-in-class area and power efficiency. Given the exceptional performance and features of BoW, it received strong support at OCP and was later adopted as the chiplet interconnect of OCP on organic substrates as well as advanced packaging. Nulink technology not only led to creation of BoW at OCP, but the signaling/clocking scheme and PHY architecture also became the foundation for UCIe, which is proposed and adopted by a broad cross-section of industry heavyweights. Given the history of Nulink and its myriad similarities with UCIe, Eliyan is on the fastest path to the highest-performance UCIe compliant interconnect.

Eliyan In the News

Eliyan Closes $40M Series A Funding Round and Unveils Industry’s Highest Performance Chiplet Interconnect Technologies

Tapeout of Chiplet Connectivity Technology in 5nm Process Confirms Major Bandwidth, Power, Latency Advantages for UCIe-Compliant Die-to-Die Connectivity

SANTA CLARA, Calif. – November 8, 2022

Eliyan Corporation, credited for the invention of the semiconductor industry’s highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

About Us

Eliyan’s experienced team has built enterprise and server class chips more than 30 years. They are a combination of PHY designers and chip architects that have a deep understanding of systems and built generations of semiconductor products.
Ramin Farjadrad

Ramin Farjadrad

Co-founder & CEO

Ramin Farjadrad is the inventor of over 130 granted and pending patents in communications and networking. He has a successful track record of creating differentiating connectivity technologies adopted by the industry as International standards (Two Ethernet standards at IEEE, one chiplet connectivity at OCP.) Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and Aquantia, which IPO’d and was acquired by Marvell Technologies. Ramin’s Ph.D. EE is from Stanford.

Patrick Soheili

Patrick Soheili

Co-founder & Head of Business and Corporate Development

Patrick Soheili has been CEO of three early-stage technology companies.  He led BD/CD and IPBU at eSilicon, as well as heading marketing, sales, and operations management at Altera, AMD, and TRW. He’s led seed-stage deep technology venture capital resulting in multiple IPOs and M&As. Patrick’s MBA is from Purdue; his Math and Physics BS is from UCSB and the University of Bristol.

 

Syrus Ziai

Syrus Ziai

Co-founder & VP of Engineering

Syrus Ziai held VP of engineering roles at Nuvia, Ikanos, Qualcomm, and PsiQuantum. He has a breadth of experience in systems, chip architecture, design methodologies, and packaging, and has managed 100+ engineering teams across the semiconductor industry.

Syrus’s MS EE is from Stanford. He has 30 years of experience and has developed 11 patents.

Board Members

Shaygan_Kheradpir_Cerberus

Cerberus Capital Management

Ramin Farjadrad

Ramin Farjadrad

Eliyan

Patrick Soheili

Patrick Soheili

Eliyan

Celesta Capital

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