Our Products
Eliyan’s NuLink™ PHY technology achieves exceptional performance on standard packaging that others can only deliver using advanced packaging, and enables extreme high performance on advanced packaging that outperforms competing solutions.
NuLink is the building block for Eliyan’s die-to-die (D2D) and die-to-memory (D2M) PHY IP core products. NuLink-X is the building block for Eliyan’s chip-to-chip (C2C) IP core products.
Together, NuLink D2D and NuLink-X C2C provide the foundation for Eliyan’s Chiplet products that help enable a broad range of semiconductor solutions.
NuLink PHY IP Core Products
Eliyan uses NuLink technology to deliver low-power and high-performance die-to-die (D2D) IP core products to connect ASICs on the same package substrate. Eliyan uses NuLink-XS technology to deliver low-power and high-performance chip-to-chip (C2C) IP core products. Our PHY IP core products support multiple industry standards and are available on both standard packaging and advanced packaging.
Eliyan has a family of NuLink-SP high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same standard organic/laminate package substrate. Eliyan’s PHY technologies with patented implementation techniques enable the same levels of performance and power as those provided by advanced packaging options. They provide benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry standard packaging. In many applications this eliminates the need for advanced packaging technologies such as silicon interposers or silicon bridges.
Standard Package D2D PHY Products and Key Bandwidth Metrics
The NuLink PHY IP cores for standard packaging are designed for standard organic/laminate packages with bump pitches from 100um to 130um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe and BoW) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD).
NuLink-SP D2D PHY for Std Pkg @ 110um bump pitch
| Eliyan D2D Std Pkg |
NuLink UCIe Unidirectional |
NuLink UCIe Unidirectional 64Gbps |
NuLink BoW Unidirectional 64Gbps |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|---|---|
| Process Node | 5nm/3nm/2nm | 3nm/2nm | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 64 Tx + 64 Rx | |
| Data Rate/Lane | 32 | 64 | 64 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 1.8 | 3.6 | 4.1 | 4.1 | Tbps/mm |
| Area BW Metric | 1.1 | 2.3 | 3.1 | 3.1 | Tbps/mm2 |
| Reach | 50 | 50 | 50 | 5 | mm |
Eliyan has a family of NuLink-AP extremely high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same advanced package silicon interposer or via silicon bridges. Eliyan’s PHY technologies with patented implementation techniques enable improved performance and power over other solutions on advanced packaging, in order to meet the performance requirements of today’s most demanding HPC/AI applications.
Advanced Package D2D PHY Products and Key Bandwidth Metrics
The NuLink-AP PHY IP cores for advanced packaging are designed for silicon interposers and bridges with bump pitches from 40um to 55um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 128 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, UMI, SBD).
NuLink-AP D2D PHY for Adv Pkg @ 45um bump pitch
| Eliyan D2D Adv Pkg |
NuLink UCIe Unidirectional |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|
| Process Node | 4nm/3nm/2nm | 3nm/2nm | |
| # Data Lanes | 64 Tx + 64 Rx | 128 Tx + 128 Rx | |
| Data Rate/Lane | 40 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 13.2 | 21.1 | Tbps/mm |
| Area BW Metric | 9.1 | 14.6 | Tbps/mm2 |
| Reach | 2 | 2 | mm |
Eliyan has an industry-first family of NuLink-XS chip-to-chip (C2C) IP core products designed to be integrated into ASIC designs to connect two chips on separate packages across a PCB. Eliyan’s PHY technologies with patented implementation techniques enable much lower power at the same levels of performance as SerDes connections, while providing benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry-standard packaging.
C2C PHY Products and Key Bandwidth Metrics
The NuLink-XS chip-to-chip (C2C) PHY IP cores enable longer-reach C2C (vs. D2D) connections between two packaged devices on the same PCB with much lower power than 112G/224G SerDes solutions.
up to 100mm
NuLink-XS C2C PHYs for Std Pkg @ 110um bump pitch
| Eliyan C2C Std Pkg |
NuLink-XS 1.0 long-reach C2C |
NuLink-XS 2.0 long-reach C2C |
Units |
|---|---|---|---|
| Process Node | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 16 Tx + 16 Rx | 16 Tx + 16 Rx | |
| Data Rate/Lane | 32 - 40 | 64 | Gbps |
| Silicon Beachfront BW Metric | 1.0 - 1.3 | 2.0 | Tbps/mm |
| Area BW Metric | 0.75 - 0.94 | 1.5 | Tbps/mm2 |
| Reach | 100mm | 100mm | mm |
NuLight™ Chiplet Products
Eliyan developed NuLight™ optical chiplet products to break through the I/O bandwidth wall, a major limitation in HPC and AI performance today. NuLight chiplets are sold to module makers for fully-retimed optical modules (NPO/XPO).
Copper links cannot provide the bandwidth and reach needed for next-generation AI pods. Pods with 1,000 to 10,000 GPUs need both higher bandwidth per lane (>400G/lane) and longer connection reach (>10 m). There is no practical copper PHY solution above 400G/lane at 10 m. NuLight™ is a high-bandwidth optical interconnect designed to deliver copper-like reliability, supply, cost, and power for those links.
Eliyan’s NuLight platform uses a Slow-n-Wide approach: 2D micro-VCSEL arrays build high-speed links from many parallel optical lanes, rather than pushing a single lane to an ultra-high data rate. Bandwidth scales by adding optical lanes, not by increasing the speed of each lane. Multiple NRZ lanes replace one high-speed PAM4 lane, reducing design complexity, power, and latency and improving reliability.
Nexus™ Reverse Gearbox Chiplet
The Nexus reverse gearbox chiplet combines 212.5G SerDes and 53G die-to-die links. The host side is a power-reach configurable 224G-class SerDes to enable extremely low-power optical module solutions. The line side uses configurable die-to-die links to enable connections to a wide range of EIC companion chiplets with different optical technologies, including microVCSELs and microLEDs.
Oscar is a micro-VCSEL TIA-driver and photodiode-array chiplet. Together with Nexus, it forms Eliyan’s 1.6 Tbps NuLight slice for fully-retimed optical modules.
NuLight™ Platform for microVCSELs
The NuLight microVCSEL platform combines the Nexus reverse gearbox chiplet with the Oscar chiplet in Eliyan’s 1.6 Tbps NuLight platform for fully-retimed modules (NPO/XPO).
