Our Products
Eliyan’s NuLink™ PHY technology achieves exceptional performance on standard packaging that others can only deliver using advanced packaging, and enables extreme high performance on advanced packaging that outperforms competing solutions.
NuLink is the building block for Eliyan’s die-to-die (D2D) and die-to-memory (D2M) PHY IP core products. NuLink-X is the building block for Eliyan’s chip-to-chip (C2C) IP core products.
Together, NuLink D2D and NuLink-X C2C provide the foundation for Eliyan’s Chiplet products that help enable a broad range of semiconductor solutions.
NuLink PHY IP Core Products
Eliyan uses NuLink technology to deliver low-power and high-performance die-to-die (D2D) IP core products to connect ASICs on the same package substrate. Eliyan uses NuLink-X technology to deliver low-power and high-performance chip-to-chip (C2C) IP core products. Our PHY IP core products support multiple industry standards and are available on both standard packaging and advanced packaging.
Eliyan has a family of NuLink-SP high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same standard organic/laminate package substrate. Eliyan’s PHY technologies with patented implementation techniques enable the same levels of performance and power as those provided by advanced packaging options. They provide benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry standard packaging. In many applications this eliminates the need for advanced packaging technologies such as silicon interposers or silicon bridges.
Standard Package D2D PHY Products and Key Bandwidth Metrics
The NuLink PHY IP cores for standard packaging are designed for standard organic/laminate packages with bump pitches from 100um to 130um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe and BoW) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD).
NuLink-SP D2D PHY for Std Pkg @ 110um bump pitch
| Eliyan D2D Std Pkg |
NuLink UCIe Unidirectional |
NuLink UCIe Unidirectional 64Gbps |
NuLink BoW Unidirectional 64Gbps |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|---|---|
| Process Node | 5nm/3nm/2nm | 3nm/2nm | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 32 Tx + 32 Rx | 64 Tx + 64 Rx | |
| Data Rate/Lane | 32 | 64 | 64 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 1.8 | 3.6 | 4.1 | 4.1 | Tbps/mm |
| Area BW Metric | 1.1 | 2.3 | 3.1 | 3.1 | Tbps/mm2 |
| Reach | 50 | 50 | 50 | 5 | mm |
Eliyan has a family of NuLink-AP extremely high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same advanced package silicon interposer or via silicon bridges. Eliyan’s PHY technologies with patented implementation techniques enable improved performance and power over other solutions on advanced packaging, in order to meet the performance requirements of today’s most demanding HPC/AI applications.
Advanced Package D2D PHY Products and Key Bandwidth Metrics
The NuLink-AP PHY IP cores for advanced packaging are designed for silicon interposers and bridges with bump pitches from 40um to 55um. Eliyan offers NuLink PHY IP products for industry standards (including UCIe) as well as unique value-added products including UMI™ and SBD. The NuLink PHY IP cores typically have 128 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, UMI, SBD).
NuLink-AP D2D PHY for Adv Pkg @ 45um bump pitch
| Eliyan D2D Adv Pkg |
NuLink UCIe Unidirectional |
NuLink SBD Simultaneous Bidirectional |
Units |
|---|---|---|---|
| Process Node | 4nm/3nm/2nm | 3nm/2nm | |
| # Data Lanes | 64 Tx + 64 Rx | 128 Tx + 128 Rx | |
| Data Rate/Lane | 40 | 64 (2x32) | Gbps |
| Beachfront BW Metric | 13.2 | 21.1 | Tbps/mm |
| Area BW Metric | 9.1 | 14.6 | Tbps/mm2 |
| Reach | 2 | 2 | mm |
Eliyan has an industry-first family of NuLink-X chip-to-chip (C2C) IP core products designed to be integrated into ASIC designs to connect two chips on separate packages across a PCB. Eliyan’s PHY technologies with patented implementation techniques enable much lower power at the same levels of performance as SerDes connections, while providing benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry-standard packaging.
C2C PHY Products and Key Bandwidth Metrics
The NuLink-X chip-to-chip (C2C) PHY IP cores enable longer-reach C2C (vs. D2D) connections between two packaged devices on the same PCB with much lower power than 112G/224G SerDes solutions.
NuLink-X C2C PHYs for Std Pkg @ 110um bump pitch
| Eliyan C2C Std Pkg |
NuLink-X 1.0 long-reach C2C |
NuLink-X 2.0 long-reach C2C |
Units |
|---|---|---|---|
| Process Node | 3nm/2nm | 3nm/2nm | |
| # Data Lanes | 16 Tx + 16 Rx | 16 Tx + 16 Rx | |
| Data Rate/Lane | 32 - 40 | 64 | Gbps |
| Silicon Beachfront BW Metric | 1.0 - 1.3 | 2.0 | Tbps/mm |
| Area BW Metric | 0.75 - 0.94 | 1.5 | Tbps/mm2 |
| Reach | 160mm | 160mm | mm |
NuGear™ Chiplet Products
Eliyan developed NuGear chiplet products to break through the memory and I/O walls, which are major limitations in HPC and AI performance today.
HPC/AI systems have insatiable demand for data to feed compute engines, requiring extreme amounts of both memory bandwidth and I/O bandwidth. However, in the past 20 years, compute capability as measured in FLOPS has increased 100,000x while both DRAM bandwidth and I/O bandwidth has only increased by 30x, which limits the performance of HPC/AI systems. These bandwidth limitations are known as the Memory Wall and the I/O Wall.
HPC/AI applications need more memory bandwidth and capacity. Using standard HBM4 devices with 2K I/Os, XPUs can fit 2 HBMs on a 25mm side of a reticle-limited chiplet. Using NuLink-AP solutions, designers can get more bandwidth in less area and power with a custom HBM solution (using only 1K I/Os), and more capacity with a backside C2C connection to memories such as LPDDR or DDR. In another configuration, the NuLink-AP D2D can provide 2x the HBM4 bandwidth to a custom HBM with a backside port using NuLink-SP to connect to a standard package HBM. These higher bandwidth and capacity solutions greatly increase performance of HPC/AI systems.
Off-package I/O bandwidth is a significant limiter of performance in HPC/AI systems. SerDes have high power and area, and it is not desirable to integrate them directly into XPUs. When SerDes (or optical) I/O connections are made with tightly coupled chiplets on the same interposer, the achievable bandwidth is limited by the physical interposer size constraints. When I/O chiplets are moved off an interposer using NuLink-SP D2D connections, the number of SerDes or optical chiplets possible on package can be doubled, which doubles the available bandwidth to connect XPUs in a system.
NuLink D2D can be used to double the number of HBMs and I/O connections in a package substrate.
