Discover how the Universal Memory Interface tackles substrate- and die-level real-estate challenges in chiplet-based design, unlocking performance and scalability.
Eliyan’s NuLink PHY could do away with silicon interposers
While a lot of people focus on the floating point and integer processing architectures of various kinds of compute engines, we are spending more and more of our time looking at memory hierarchies and interconnect hierarchies.
Memory devices must combine new levels of capacity and power efficiency with higher performance to process the vast amounts of data required to support AI training and inference, heralding a new era of computing, said Choonhwan Kim, Senior Vice President and Head of R&D Process at SK hynix in his keynote at SEMICON Korea, January […]
Ramin is the inventor of over 130 granted and pending patents in communications and networking. He has a successful track record of creating differentiating connectivity technologies adopted by the industry as International standards (Two Ethernet standards at IEEE, one chiplet connectivity at OCP.) Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and […]
Eliyan recently taped out its NuLink die-to-die PHY IP on TSMC N3, achieving 64 Gbps per bump using standard packaging, Eliyan CEO Ramin Farjadrad told EE Times. This is equivalent to 4.55 Tbps per millimeter of bandwidth at less than half a picojoule per bit.
