SANTA CLARA, Calif. – August 24, 2023 – Eliyan Corporation, an innovator in the field of efficient chiplet interconnect, announced its support for and compatibility with the new UCIe™ (Universal Chiplet Interconnect Express™) 1.1 specification. The company has been involved with the industry-wide initiative to develop a framework for a more open and interoperable chiplet ecosystem, contributing its expertise and working to deliver the performance and bandwidth required to meet the needs of multi-die architectures.
Eliyan’s recently demonstrated the first working silicon of its NuLink PHY, implemented in a 5nm standard foundry process, requiring no advanced packaging techniques such as silicon interposers. The chip, which is compliant with existing UCIe specifications and is capable of going beyond the scope of the current specification, operates at 40Gbps/bump delivering over 2.2Tbps/mm of beachfront bandwidth at 130um pitch on standard organic packaging while meeting aggressive power and area targets. The highly area efficient NuLink™ PHY is bump limited and can deliver up to 3Tbps/mm once implemented on available standard packaging technologies at finer bump pitches, leveraging its innovative interference cancellation techniques.
Come see us at Hot Chips, August 28-29. Email us at info@eliyan.com to arrange a meeting
“The UCIe effort is a true ecosystem-based approach, and we welcome all support and input that helps move our mission forward. We appreciate Eliyan’s contributions to the evolution of the standard,” said Bob Brennan, Vice President of Customer Solutions Engineering at Intel.
“Eliyan is proud to be contributing and sharing our expertise in high-speed and power-efficient interconnect to the further evolution of the UCIe standard. The Consortium has put together an effective framework that will advance us further toward the goal of an open chiplet ecosystem and Version 1.1 of the spec includes many critical updates to enable that. As a provider of a fully UCIe compatible solution that has the flexibility to achieve even higher speeds and lower power, Eliyan looks forward to supporting and contributing to this die-to-die protocol,” said Patrick Soheili, co-founder, director and vice president of strategy and business at Eliyan.
About UCIe™ Consortium
Eliyan’s recently demonstrated the first working silicon of its NuLink PHY, implemented in a 5nm standard foundry process, requiring no advanced packaging techniques such as silicon interposers. The chip, which is compliant with existing UCIe specifications and is capable of going beyond the scope of the current specification, operates at 40Gbps/bump delivering over 2.2Tbps/mm of beachfront bandwidth at 130um pitch on standard organic packaging while meeting aggressive power and area targets. The highly area efficient NuLink™ PHY is bump limited and can deliver up to 3Tbps/mm once implemented on available standard packaging technologies at finer bump pitches, leveraging its innovative interference cancellation techniques.
About Eliyan
Eliyan Corporation is leading the chiplet revolution, focusing on a fundamental challenge with scaling semiconductor performance, size, power, and cost to meet the needs of high-performance computing applications, from desktop to datacenter. It has developed a breakthrough method to enable the industry’s highest performing interconnect for homogenous and heterogenous multi-die architectures using standard packaging substrates, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. The company’s Bunch of Wires (BoW) technique, invented by founder Ramin Farjadrad and proven to increase performance by 2x and reduce power in half in advanced process technologies, provides a more efficient approach to developing chiplet-based architectures – which are the pathway to the continued scaling of Moore’s Law. More information can be found here. www.eliyan.com
For more information, contact:
Mike Sottak
mike@wiredislandpr.com
650-248-9597